Syllabus for

Harvard Extension School CSCI E-93 (formerly CSCI E-287)

Computer Architecture (24414)

Spring 2016
Site last revised 9:46 AM 6-Jun-2016

Dr. James L. Frankel


After the upcoming Spring 2016 semester, the next time CSCI E-93 will be offered is in the Fall 2017 semester.

Before 6 PM ET on Tuesday, May 10, 2016, send the URL of your presentation to the course staff and, if you're a distance student who is not going to be present in the classroom, your logname for either Skype or Google Hangouts.

All students making a final project presentation in the last class meeting need to send e-mail to the course staff requesting a slot.

REMINDER: Please bring a laptop with your presentation slides, your block diagram, your instruction set description, Quartus, your assembler, your simulator, your VHDL code, and your assembler code -- all ready to be loaded into a DE2-70 or DE2-115, as appropriate -- to your final project presentation. We'll furnish all the Altera hardware.

There are new CSCI E-93 Application Notes on the web site.

IMPORTANT: Clock divider signals to the memory subsystem.
We believe that we have identified (thanks to Stephen Benjamin) a problem with the serial port in the memory subsystem. The serial port stops responding to both transmit and receive operations when the LSB of the clock divider is set. To repeat, the problem seems to occur only when the least-significant bit of the clock divider "clock_divide_limit" is set (see the documentation for the memory subsystem) independent of the state of the other bits in the clock divider.
Until this problem has been corrected, please do not set the least-significant bit of the clock divider.

Final Project Presentation Slots:
Time Slot Available
6:30 PM - 6:45 PM Slot 1 Filled by Nathan
6:45 PM - 7:00 PM Slot 2 Filled by Pandelis
7:00 PM - 7:15 PM Slot 3 Filled by Stephen Benjamin
7:15 PM - 7:30 PM Slot 4 Filled by Fuk
7:30 PM - 7:45 PM Slot 5 Filled by Satyam
7:45 PM - 8:00 PM Slot 6 Filled by Mark Warren
8:00 PM - 8:15 PM Slot 7 Filled by Ansuman
8:15 PM - 8:30 PM Slot 8 Filled by Stephen Karger
8:30 PM - 8:45 PM Slot 9 Filled by Ashish
8:45 PM - 9:00 PM Slot 10 Filled by Lena
9:00 PM - 9:15 PM Slot 11 Filled by Chris
9:15 PM - 9:30 PM Slot 12 Open
9:30 PM - 9:45 PM Slot 13 Filled by Pavan
9:45 PM - 10:00 PM Slot 14 Filled by Enrique
10:00 PM - 10:15 PM Slot 15 Filled by Ricardo
10:15 PM - 10:30 PM Slot 16 Filled by Jesse
10:30 PM - 10:45 PM Slot 17 Open

The Final Project problem set has been updated.

The desciption of the flushing operations has been clarified in the specification for the interface to terminal I/O.

Problem Set 4 is now due at midnight on Sunday, April 3, 2016.

There is a new CSCI E-93 Application Notes for using the Altera FPGAs section on the web site.

The Hazards and Glitches slides have been updated. In particular see post in Piazza.

The class ski trip will take place on Sunday, March 20, 2016. Reserve the date! Significant others are welcome to join. More information will follow.

Updated observations are now part of the posted MIPS Datapath - Single Memory - No Pipelining slides.

New slides for Gray Codes & Karnaugh Maps have been posted.

New links have been added for Microsoft student pricing and evaluation software.


Quick Links:

  • Class Hours & Location
  • Distance Learning Links
  • Prerequisites
  • Brief abstract
  • Overview
  • Books/Course Bibliography
  • Instructor
  • Teaching Assistants
  • Grading
  • Plagiarizing
  • Approximate Schedule
  • Hardware Related References
  • Course Documents On-Line
  • Tuesdays 7:40-10:15 PM in 53 Church Street, Room L01.

    Distance Learning Links:

    During Class:

    Live video stream (during class meeting)

    Chat room (during class & section meetings)

    After Class:

    Videos of class and section are available on the course's Canvas web site under Lecture Video.

    Midterm Exam

    Our midterm exam is a three hour long proctored exam. Students who live within the six-state New England area (Connecticut, Maine, Massachusetts, New Hampshire, Rhode Island, and Vermont) must come to campus to take the exam (of course, any student may choose to come to campus to take the exam). Students who do not take the exam on campus in our classroom are required to procure the services of a Harvard-approved proctor as described in That document states that the exam must be taken "within a specific 24-hour period." In our case, the 24-hour period starts on the date and time of our in-class exam and ends 24 hours later. That is, the exam must be started within that 24-hour period.

    The exam allows open-book access to *only* the three required textbooks. No notes are allowed. No electronic devices are allowed.


    Knowledge of data structures and programming experience CSCI E-22 (formerly CSCI E-119) (Data Structures) with some background in boolean/digital logic preferred, but not required ENSC E-123 (Laboratory Electronics: Digital Circuit Design) or equivalents.

    Brief abstract:

    A study of the fundamental concepts in the design and organization of modern computer systems. Topics include computer organization, instruction set design, processor design, memory system design, timing issues, interrupts, microcoding, and various performance-enhancing parallel techniques such as prefetching, pipelining, branch prediction, superscalar execution, and massive-parallel processing. Study of existing architectures using CISC, RISC, vector, data parallel, and VLIW designs. An extensive lab project will be required of all students.

    4 credits. Noncredit, undergraduate, and graduate credit.


    Computer Science E-93 is a comprehensive course in the architecture and organization of modern computers. Students are already expected to be comfortable with designing, coding, and debugging programs of modest complexity while employing good programming style, structured techniques, and employing appropriate data structures as appropriate. In particular, this class is not a programming course, but students will be required to write several significant programs. In addition, some experience with digital logic and gates and with programming in assembler language is preferred.

    A significant portion of the class will involve the design and implementation of a major term project. The project will be developed by each student working alone. That project is the core of a new computer's central processing unit including the data path, instruction fetch and decoding unit, and registers implemented using an Altera FPGA. Initially, both the classroom lectures and the section meetings will be covering material important to the design and implementation of the final project. Later in the semester, advanced topics will be covered in class; however, both the class and sections will continue to support students as term projects progress. Throughout the semester, students will be working on and debugging their projects leading to their complete implementation and demonstration.

    Because the course requires a significant term project involving both programming and hardware implementation, the assignments will be time-consuming; therefore, a significant time commitment to the course is necessary. Although the relevant experience of students in the class is usually quite diverse, depending on background, it is not unusual for students to spend 15-20 hours per week or more completing the readings and homework assignments. Although the computers are available more-or-less around the clock, occasionally they will suddenly become unavailable (this is known as a crash). As with all such events, they always seem to occur at the worst possible time. Plan your computer work so that it is complete in advance of the deadlines. You have now been forewarned!

    Books/Course Bibliography:

    All course books are available from the Harvard Coop and are on reserve at Grossman Library.

    Required Textbooks:

    Contemporary Logic Design, Second Edition; Randy H. Katz and Gaetano Borriello; Prentice Hall Inc., 2005; ISBN-13 978-0-201-30857-0; ISBN-10 0-201-30857-6; Errata for the Second Edition

    Computer Organization and Design: The Hardware/Software Interface, Fifth Edition; David A. Patterson and John L. Hennessy; Morgan Kaufmann/Elsevier, September 2013; ISBN-13 978-0-12-407726-3; Errata for the Fourth Revised Edition; Errata for the Fifth Edition

    The Designer's Guide to VHDL, Third Edition; Peter J. Ashenden; Morgan Kaufmann/Elsevier, May 2008; ISBN-13 978-0-12-088785-9; ISBN-10 0-12-088785-1; Errata for the Third Edition

    Optional Additional Digital Electronics Book:

    Digital Systems: Principles and Applications, Eleventh Edition; Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss; Prentice Hall Inc., 2011; ISBN-13 978-0-13-510382-1; ISBN-10 0-13-510382-7

    Optional Electronics Books:

    The Art of Electronics, Third Edition; Paul Horowitz and Winfield Hill; Cambridge University Press, April 2015; ISBN-13 978-0521809269

    The Art of Electronics Student Manual; Thomas C. Hayes and Paul Horowitz; Cambridge University Press, September 1989; ISBN-13 978-0521377096; ISBN-10 0521377099

    Optional Additional Computer Architecture Books:

    Computer Architecture: A Quantitative Approach, Fifth Edition; John L. Hennessy and David A. Patterson; Morgan Kaufmann/Elsevier, September 2011; ISBN 978-0-12-383872-8

    MIPS RISC Architecture, Second Edition; Gerry Kane and Joseph Heinrich; Prentice Hall Inc., 1992; ISBN-13 978-0-13-590472-5; ISBN-10 0-13-590472-2

    Modern Operating Systems, Fourth Edition; Andrew S. Tanenbaum; Prentice Hall Inc., 2015; ISBN-13 978-0-13-359162-0; ISBN-10 0-13-359162-X

    Optional VHDL Book:

    Fundamentals of Digital Logic with VHDL Design with CD-ROM, 3rd Edition; Stephen D. Brown and Zvonko G. Vranesic; McGraw-Hill Higher Education, 2009; ISBN-13 978-0-07-722143-0; ISBN-10 0-07-722143-5. This book includes a CD-ROM with the student edition of Altera's MAX+PLUS II CAD software. There is also a website for this book.

    There will also be other handouts & supplementary readings


    Dr. James L. Frankel Dr. Frankel's Photo,

    Teaching Assistants:

    Each student is assigned to a Teaching Assistant (TA). Each TA holds weekly sections and office hours as described below. Attendance at your TA's section is strongly recommended. Although your TA should be your primary point of contact for questions and issues, you are welcome to attend another TA's section and/or office hours in addition.

    TA Section Meeting Time & Place Office Hours Time & Place E-mail & Phone
    Daniel Willenson  Daniel's Photo,
    Section Site
    6:30-7:30 PM ET,
    1 Story Street, Room 307
    Monday, 7:30-8:30 PM by appt. only,
    Science Center, Room 101e
    E-mail: Daniel's e-mail address; +1.571.265.2932 (9:00 AM - 9:00 PM). If there's no answer, please leave a message with your name and a call-back number.
    Mark Ford
    Mark's Photo,
    Section Site
    6:30-7:30 PM ET,
    1 Story Street, Room 307
    6:30-7:30 PM ET by appt. only,
    Science Center, Room 101e
    E-mail: Mark's e-mail address; +1.978.496.7213 (1:00 PM - 9:00 PM ET) If there's no answer, leave a message and a call-back number


    Graduate-credit students:

    All problem sets and programming assignments are due at midnight on Sunday night (i.e., midnight between Sunday and Monday) Eastern Time (unless otherwise stated in the assignment or in the syllabus). Unless otherwise stated, all programming assignment solutions must be written in C, C++, or Java, have run under Cygwin, under MacOS, or on one of the Linux/Ubuntu 64-bit x86 computers (collectively accessible via in the Science Center or on the Altera DE2-70 or DE2-115 FPGA system, as appropriate, be submitted using "git" on (or, in dire circumstances, via e-mail only if agreed to by your TA), be well-written (clear coding style, modular structure, appropriately commented and documented in English), and tested (include any programs and/or shell scripts used in testing your solution and a transcript showing your program being tested (using the "script" program or equivalent) as part of your submission). In addition, each submission must include a makefile to build the assignment. The grade for programming assignments will include all of these attributes. (Of course, the solutions may be written and tested using any system of the student's choosing; however, when the solution is complete, it must be pushed to the git code repository on Also, in addition to using code development tools under Cygwin or MacOS, you may use the "nice" course computers and test your code there! We will be grading the solutions based on their behavior under Cygwin, MacOS, or on the Harvard "nice" computers.) The Science Center computers may be accessed using "ssh" over the Internet. Files may be transferred to these systems using "secure ftp" (SFTP). The SecureCRT and SecureFX programs are available from the Science Center at; these programs implement "ssh" and "secure ftp," respectively. Remember, in addition to handing in all parts of the problem set solution or programming assignment program, sample runs of the program which demonstrate that the program works must be attached.

    A late homework will lose 5% of its original grade for each day it is late (e.g. an assignment handed in two and a half days late will receive its original grade multiplied by 0.85). Late assignments may be submitted via "git" and an e-mail message notifying the instructor and your teaching assistant should be sent immediately after the late assignment is submitted. In addition, each student is given five free late days that may be used freely during the semester. However, keep in mind that almost all of the assignments are built on the previous assignments; handing in one assignment late does not extend the due date for subsequent assignments. The scope and difficultly level of the assignments increases during the class; therefore, we recommend against using the five free late days early in the class.

    In the preceding paragraph, the phrase "commented and documented" is used; this paragraph will clarify the necessary comments and documentation that should be provided with all programs. First, there should be a description of the entire application. This should include the user interface (i.e., how a user interacts with the program) and an explanation of what the program does. This documentation may be in a separate file from the program itself. Second, there should be a description at the beginning of each file which outlines the contents of that file. Third, each routine, function, method, etc. must be preceded by a section describing: (1) the name of the routine, (2) the purpose/function of the routine, (3) the parameters to the routine (name, type, meaning), (4) the return value from the routine (type, meaning), and (5) any side-effects (including modifying global variables, performing I/O, modifying heap-based storage, etc.) that the routine may cause. Fourth, declarations of variables should be commented with their purpose. Fifth, blocks of code should be commented to describe the purpose of the code section. Sixth, any complex or difficult to understand code statements or fragments should be commented to clarify their behavior.

    In addition to programming in conventional languages (either C, C++, or Java), students will learn how to write code in VHDL. This is the Hardware Description Language that we will use to configure the Altera FPGA. All students are required to use the Altera Quartus II Web Edition Software, Version 13.0, Service Pack 1, released June, 2013. This software may be downloaded from the Altera web site, is free, and no license is required. The software runs only on either Windows or Linux. The specific version of Altera Quartus software that students should use may be updated during the class term.

    When using "git" and, make sure that your cloned repository is appropriately shared with your TA and the instructor. Information on using "git" and setting up your repository is available on the section web site. Tag each of your submissions as follows; specify "questionnaire" for the course questionnaire, specify "ps1-submit" for Problem Set 1, "ps2-submit" for Problem Set 2, etc., specify "prelim-term-project" for the Preliminary Final Project Problem Set, and specify "term-project" for the Term Project.

    Our midterm exam is a three hour long proctored exam. Students who live within the six-state New England area (Connecticut, Maine, Massachusetts, New Hampshire, Rhode Island, and Vermont) must come to campus to take the exam (of course, any student may choose to come to campus to take the exam). See Distance Learning Links: Midterm Exam for more information for distance students.

    The exam allows open-book access to *only* the three required textbooks. No notes are allowed. No electronic devices are allowed.


    All work should be the personal creation of the individual student. Students are free to consult with each other and to study together, but all problem set solutions, programming assignments, exams, and the final project must be the personal contribution of each individual student. More explicitly, whenever a concept is reduced to a detailed algorithm or a program, no collaboration is allowed. If a paper, assignment, exam, program, or final project contains any information, algorithms, program fragments or other intellectual property taken from another source, that source and material must be explicitly identified and credit given. If you have any questions about this policy, it is the student's responsibility to clarify whether their activity is considered plagiarism.

    Approximate Schedule:

    November 2015 Description
    12 Online registration opens for degree candidates
    16 Registration opens for all students
    25-29 Thanksgiving Break


    December 2015 Description
    22-January 3, 2016 Winter Break


    January 2016 Description
    18 Martin Luther King Jr. Day
    24 Registration ends
    25 Classes begin
    26 Introduction, course information & policies, outline, schedule. Review of simple digital logic.
    31 at Midnight Problem Set 0 (the course questionnaire) due.


    February Description
    1 Late registration (with $50 late fee) ends; last day to drop with full-tuition refund; last day for course and credit status changes
    2 Flip-flops as memory building blocks. Advanced Boolean logic, computer arithmetic, useful laws and theorems, sum of products form, minimization, technology metrics.
    For today, read Katz chapters 1 and 2 and Patterson/Hennessy appendix B (4/e revised printing: appendix C) on The Basics of Logic Design.
    8 Last day to drop with half-tuition refund
    9 Place values, numeric encodings, gray codes & Karnaugh maps, canonical forms (minterms & maxterms), dealing with time in combinational logic networks, MIPS assembly language programming and instruction set design, addressing modes.
    For today, read Katz chapter 3 and Patterson/Hennessy chapters 1 and 2 (4/e revised printing: chapters 1 and 2) on Computer Abstractions and Technology, and Instructions: Language of the Computer.
    14 at Midnight Problem Set 1 due.
    15 President's Day.
    16 Designing a processor: the datapath and control logic, Continue to discuss the MIPS instruction set and a simple block diagram of its implementation.
    For today, read Katz chapter 4 and Patterson/Hennessy chapter 4 (4/e revised printing: chapter 4) on The Processor.
    23 Discuss the instruction sets for the PDP-8 and the PDP-11.
    For today, read Katz chapters 5 and 6 and Patterson/Hennessy chapter 3 (4/e revised printing: chapter 3) on Arithmetic for Computers.
    28 at Midnight Problem Set 2 due.


    March Description
    1 Waveform diagrams, glitches, and hazards. Complete the PDP-11 instruction set including subroutines and condition codes. Endianness. Finite state machines. Material to be covered in the midterm exam. Distribute Altera/Terasic hardware.
    For today, read Katz chapters 7 and 8.
    8 Midterm exam.
    For today, read Patterson/Hennessy chapter 5.6-5.18 (4/e revised printing: chapter 5.4-5.14) on the memory hierarchy.
    13-20 Spring Break.
    13 at Midnight Problem Set 3 due.
    22 Review the midterm exam. Details of implementing an assembler. MIF file description. Performing I/O operations using memory-mapped I/O. The interface to our memory subsystem.
    For today, read Patterson/Hennessy appendix A (4/e revised printing: appendix B) on Assemblers, Linkers, and the SPIM Simulator and Patterson/Hennessy chapter 5.2, 5.11 (4/e revised printing: chapter 6) on I/O devices.
    27 at Midnight Problem Set 4 due.
    29 Serial communication, Caching, Virtual memory.
    For today, read Patterson/Hennessy chapter 5.1-5.5 (4/e revised printing: chapter 5.1-5.3) on caches.


    April Description
    5 Virtual memory (continued), TLB's (Translation Lookaside Buffers), Page Replacement strategies, Basic electronics, Pipelining.
    10 at Midnight Problem Set 5 due.
    12 Pipelining (continued). Parallelism. SISD, SIMD, & MIMD architectures. Locality of data to processor.
    For today, read Patterson/Hennessy chapter 6 (4/e revised printing: chapter 7) on parallel processing.
    17 at Midnight Preliminary Final Project Problem Set due.
    19 VLSI circuit (custom silicon) design.
    22 Last day to withdraw with no tuition refund and with course on record with WD/WN (withdrawal) grade
    24 at Midnight Problem Set 6 due.
    26 I/O (Input/Output) Systems, interrupts. Vector computers. Data parallel computers.


    May Description
    3 RISC vs. CISC architectures. VLIW (Very Long Instruction Word) computers. Mapping a high-level language onto a low-level architecture.
    9-14 Final Exam Period and Last Class Meetings
    10 Final Class Meeting during usual section and class time. Student project presentations/demonstrations. Term Project due.
    13 by 2 PM ET All Final Project code, documentation, and presentation material must be submitted.
    25 Grades available online.
    26 Commencement.
    30 Memorial Day.

    Hardware Related References:

    Altera Information:

    The class project will use the Altera Cyclone II FPGA (EP2C70F896C6N) on our Altera Development and Education DE2-70 boards (or alternatively, the Altera Cyclone IV FPGA (EP4CE115F29C7) on DE2-115 boards). Students taking the course in person in Cambridge will be able to borrow the hardware for use during the semester. Distance students must purchase their own Altera DE2-115 Development and Education Board. This hardware is available at academic pricing from the Terasic web site.

    Altera information is available for:

    As stated on the Altera web site, Quartus II version 13.0sp1 supports all Altera University Program FPGA boards, including our DE2-70 and DE2-115 boards. This is the version of Quartus II that we will all be using in the class. Although new versions of the Quartus II software will be developed and released each year by Altera, Quartus II V13.0sp1 will continue to be maintained and updated for the foreseeable future.

    The Quartus II software starting from version 13.1 does not include support for the Cyclone II family of FPGAs, which are used in DE2-70 boards. Note that the DE2-115 board uses the Cyclone IV family, and so is not affected.

    In addition, starting in Quartus II version 14.0 there will no longer be support for 32-bit computers (Quartus II V14.0 can only be used on 64 bit computers).

    Older class projects used the Altera FLEX 10K device (EPF10K70RC240-4) on Altera University Program UP2 boards. Support for the Altera FLEX 10K device family has been removed from Quartus II software version 9.1 and future releases. The last support for these device families is version 9.0 SP2, which will be available permanently on Altera's Download Center.

    When we were using the UP2 Education Board, the programming cable that we used was the USB Blaster Cable manufactured by Terasic, but it is identical to the Altera USB-Blaster and uses the same drivers.

    Altera information is available for:

  • the Altera UP2 Education Board,
  • the Altera University Program UP2 Education Kit, User Guide,
  • the ByteBlaster II User Guide,
  • the ByteBlasterMV User Guide,
  • the USB-Blaster User Guide,
  • the Installation of Altera Programming Cable Drivers,
  • the Altera University Program Design Software (Quartus II Web Edition Software),
  • the Altera Quartus II Web Edition Software,
  • the Altera Software Installation and Licensing Manual for Windows,
  • the Quartus II Development Software Literature including the Quartus II Handbook v12.1.0 (Complete Three-Volume Set), and
  • the Quartus II Web Edition Licensing (no longer needed).

    Sample Altera VHDL documents are:

    CSCI E-93 Application Notes for using the Altera FPGAs:

    Laboratory Documents and Programs:

    USB to Serial Adapter:

    Static dissipative devices used in the lab:

    The ring terminal at the end of the common point ground wire should be attached to the nearest electrical outlet faceplace using the screw between the outlets of a duplex outlet. Note that the alligator clips connected to the wires on both the anti-static mat and the wrist strap are removeable. The alligator clips are actually adapters from banana plugs to alligator clips similar to the Mueller Electric BU-60. After the alligator clip adapter is pulled off, the banana plug can be plugged into one of the two banana jacks on the common point ground.

    Course Documents On-Line:

    Slides used in class are available on-line:

    The course questionnaire is available on-line.

    The class problem sets are also available:

    A Piazza Wiki/Forum (on-line discussion list) for CSCI E-93 is set up at Harvard Extension School CSCI E-93 Piazza Forum.

    Look here for information about the GNU Project and the Free Software Foundation.

    Look here for information about getting GNU Emacs for Windows 95/98/ME/NT/XP and 2000.

    Look here for information about getting the Cygwin UNIX environment for Windows.

    Look here for Unix distributions.

    You can purchase a copy of Visio at discounted student pricing. In addition, other Microsoft Office products are available at academic prices. To qualify as a student you must have a valid e-mail address at an educational institution ending with the domain suffix .EDU (i.e., OR have a valid email address at one of the educational institutions listed on Microsoft's web site AND you must be a student at a U.S. educational institution and must be actively enrolled in at least 0.5 course credit and be able to provide proof of enrollment upon request. Follow this link for Microsoft student pricing. In addition, you can download a free 60-day evaluation version of Visio 2016 and other Microsoft products. Follow these links for Microsoft Visio, Microsoft Visio Professional 2016. Through your company, you may be able to participate in the Microsoft Home Use Program that will entitle you to purchase Office Professional Plus 2016, Visio Professional 2016, and Project Professional 2016 for $9.95 each. Additionally, the Home Use Program entitles you to purchase backup DVDs for $15.95 each.

    Dia is a GTK+ based diagram creation program for GNU/Linux, Unix, and Windows. It is released under the GPL license. Click here for the homepage for Dia. The Windows version is available for download here. The Linux version is available for download here.

    OmniGraffle is a diagramming and graphic design program for Mac OS X and iOS. is an online diagram software/flowchart maker, built around Google Drive(TM), that is designed to replace Visio(TM) in your Google Drive based office setup. enables you to draw flowcharts, org charts, wireframes, UML, mind maps and more, then save them to your Google Drive. It uses the Google Drive Real Time collaboration functionality, so multiple users can work on the same diagram simultaneously. is permanently free for all personal Google accounts, as well as Google for Educational accounts and for charitable usage. Pricing for Google for Work domains can be found at

    Further information is available about SPIM, the MIPS assembly language simulator.

    Electronics stores in the Greater Boston Area:

    Electronics distributors on the Web:

    Hardware distibutors on the Web:

    Harvard University Information Technology:

    Section specific home page is available: