Preliminary Final Project Problem Set
Harvard Extension School CSCI E-93:
Computer Architecture
Spring 2019
Due: April 7, 2019 at Midnight
Total of 50 Points
This assignment will count toward the grade for the final project not
toward the grade for problem sets.
For this assignment, based on your architecture design from Problem
Set 2 with appropriate modifications made by you based on comments and
design changes, complete the following assignment.
Please submit your solution to this problem set using "git" with named
branch prelim-term-project.
Produce VHDL code for the ALU (Arithmetic Logic Unit) of your final
project. Your ALU should be built from an elementary bit-slice design
in which your ALU operations are constructed from simple Boolean logic
gates (e.g., do *not* use the VHDL add operator, +, on integers to
construct your adder). Of course, you are able to use all the basic
Boolean operators in VHDL such as and, or, not, xor, xnor. The ALU
should be able to perform all operations required by your instruction
set/block diagram.
Please include with this assignment an up-to-date copy of your
processor's block diagram and an up-to-date copy of your processor's
instruction set.
Last revised 9-Jan-19